Consumer electronics are decreasing in size and increasing their use of laser diodes that emit into the environment. For example, 3D gesture recognition applications of high field of view near infrared laser diodes are appearing within consumer devices such as televisions, tablets and mobile devices. It would be advantageous to decrease the size of laser diode packages to allow them to be more easily included in such devices.
Wafer level Packaging (WLP) is a process for packaging a die, chip, integrated circuit (IC) or other semiconductor device using wafer level processing techniques to fabricate a plurality of packages in each wafer then separate the individual packages. Wafer level packaging is distinct from chip level packaging because the WLP process is applied to a plurality of packages simultaneously on a wafer or wafers while chip level packaging processes are applied to each chip or package individually.
Chip level packaging can occur on wafers, for example individually placing, aligning and attaching a component for each chip or package on the wafer. This is not considered wafer-level packaging because the placing, aligning and attaching process must be repeated for each component for each package instead of managing the placing, alignment and attaching of all copies of the component simultaneously.
An example of a chip level packaging process for edge-emitting laser diodes is described in U.S. patent publication 2013/0022069 published Jan. 24, 2013 in the name of Lee et al., owned by the present Applicant, and incorporated herein by reference for all purposes. In Lee et al., the reflective sidewalls and optical elements such as a diffuser or lens are individually aligned and secured for each package.
Attachment of optical components, such as diffusers, at the chip level has been in practice for some time; however, individually aligning and attaching components of each package is costly, time consuming, and prone to misalignments due to the nature of manual dispensing. Generally, costs decrease when more steps of the packaging process and more components of the package can be fabricated and attached in bulk at the wafer-level rather than individually at the chip level. It would be advantageous to reduce the use of chip level processing of components when producing vertically turned edge-emitting laser diode packages.
An example of a wafer level packaging process for edge-emitting laser diodes is described in U.S. Pat. No. 6,998,691 issued Feb. 14, 2006 to Baugh et al. and incorporated herein by reference for all purposes. In Baugh et al., a cap wafer includes a plurality of caps, each being a cavity containing a reflector. An optically transparent submount wafer includes a plurality of submounts, each having an attached laser diode, electrical traces and vias connecting the diode to external terminals and a focusing lens. The cap wafer is attached above the submount wafer such that each laser diode is contained within a cavity. Horizontally emitted light from the edge-emitting laser diode reflects off the cap's reflector and passes vertically down through the lens and the transparent submount to exit the package. However, the submount in Baugh et al. is complex to fabricate because it must provide electrical connectivity for the emitter outside the package, it must secure the emitter within the package, and it must provide optical transmission through the submount and out of the package. According to Baugh et al., the submount wafer is predominantly transparent to light from the laser diode making the submount a particularly expensive component of the package. Furthermore, the lens or other optical elements in the submount focus the emitted light, such as for fiber optic transmissions and do not address the problem of distributing light over a large field of view.
The present disclosure seeks to overcome some of the disadvantages of the prior art.